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october 2015 ? 20 15 f airchild semiconductor corporation www.fairchildsemi.com FL7921R ? rev. 1 . 1 f l7921r in tegrated critical - mode pfc and quasi - resonant current - mode pwm lighting controller fl 7 921r integrated critical - mode pfc and quasi - resonant current - mo de pwm lighting controller features ? integrated pfc and flyback controller ? critical - mode pfc controller ? zero - current detection for pfc stage ? quasi - resonant operation for pwm stage ? internal minimum t off 8 s for qr pwm stage ? internal 10 ms soft - start for pwm ? brownout protection ? high / low line over - power compensation ? auto recovery over - current protection ? auto recovery open - loop protection ? auto recovery over - temperature protection ? adjustable over - temperature with external ntc through the rt pin ? auto recovery vdd pin and output voltage ovp applications ? medium to high power led lighting driver application description the highly integrated FL7921R combines a power factor correction (pfc) controller and a quasi - resonant pwm controller. integration provides cost - effect design and allows for fewer external components. for pfc, FL7921R uses a controlled on - time technique to provide a regulated dc output voltage and to perform natural power factor correction. an innovative thd optimizer reduces input current distortion at zero - crossing duration to imp rove thd performance. the pfc function is always on regardless of the pwm stage load condition to ensure that high pf can be achieved at light load condition. for pwm, FL7921R provides several functions to enhance power system performance: valley detection, green - mode operation, high / low line over - power compensation. protection functions include secondary - side open - loop and over - current with auto - recovery prot ection, external recovery triggering, adjustable over - temperature protection through the rt pin and external ntc resistor, internal over - temperature shutdown, vdd pin ovp, det pin over - voltage for output ovp, and brown - in / out for ac input voltage uvp. all protections are auto recovery mode except pwm current sense pin open protection . the FL7921R controller is available in a 16 - pin, small - outline package (sop). ordering information part number protection mode operating temperature range package packing method fl 7 921r mx recovery - 40 c to + 1 2 5 c 16 - pin, small - outline package (sop) tape & reel ? 20 15 f airchild semiconductor corporation www.fairchildsemi.com FL7921R ? rev. 1 . 1 2 f l7921r in tegrated critical - mode pfc and quasi - resonant current - mode pwm lighting controller application diagram figure 1. typical application + - v o r a n g e 1 2 3 4 5 6 7 8 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 c o m p i n v c s p f c c s p w m o p f c v d d o p w m h v n c z c d v i n r t f b d e t g n d n t c n b o o s t n c z d r c z d r h v r v i n 2 c d d 1 c d d 2 c i n f 2 r g 1 r g 2 r c s 1 c c o m p q p f c r c l a m p c c l a m p r d e t 1 r d e t 2 r r t c r t c f b n p n s n a r c s 2 b c m b o o s t p f c q u a s i - r e s o n a n t f l y b a c k c p f c _ v o q p w m f l 7 9 2 1 r r i n v 1 r i n v 2 r r a n g e v a c c i n f 1 c v i n r v i n 1 ? 20 15 f airchild semiconductor corporation www.fairchildsemi.com FL7921R ? rev. 1 . 1 3 f l7921r in tegrated critical - mode pfc and quasi - resonant current - mode pwm lighting controller internal block diagram figure 2. functional block diagram c s p w m 2 1 6 7 3 4 1 1 5 1 0 9 1 2 1 3 1 8 6 1 4 2 . 5 v i n v 2 . 3 5 v c o m p 0 . 4 5 v c s p f c b l a n k i n g c i r c u i t 0 . 8 2 v s a w t o o t h g e n e r a t o r / t o n - m a x t h d o p t i m i z e r m u l t i - v e c t o r a m p . z c d o p f c d r v d r v g n d 1 0 v 2 . 1 v / 1 . 7 5 v i n h i b i t t i m e r p f c z e r o c u r r e n t d e t e c t o r v d d t w o s t e p s u v l o 1 8 v / 1 0 v / 7 . 5 v i n t e r n a l b i a s r e c o v e r y o v p u v p d i s a b l e f u n c t i o n 0 . 2 v r e s t a r t e r p f c c u r r e n t l i m i t 1 5 . 5 v l a t c h e d o r r e c o v e r y 1 7 . 5 v o p w m d e t f b r t v i n h v r a n g e i h v d e b o u n c e 1 0 0 m s 2 . 1 v / 2 . 4 5 v p f c r a n g e c c o n t r o l 1 v / 1 . 3 v 2 . 7 5 v 2 . 6 5 v 2 . 7 5 v r a n g e 2 . 9 v r a n g e 4 . 2 v 2 r r d e b o u n c e t i m e 1 0 0 a s o f t - s t a r t 1 0 m s p w m c u r r e n t l i m i t i n t e r n a l o t p r e c o v e r y 1 1 0 s 1 0 m s 0 . 8 v 0 . 5 v i r t p r o g . o t p / e x t e r n a l l y t r i g g e r i n g b l a n k i n g c i r c u i t b r o w n o u t q q s e t c l r s r q q s e t c l r s r v b & c l a m p v c o m p t o 1 . 6 v f b o l p t i m e r 5 0 m s v b o v e r 0 p o w e r c o m p e n s a t i o n s t a r t e r 2 . 2 5 m s 2 8 s 1 5 n c 2 4 v o v p 1 . 2 v v i n v s t a r t u p s / h t o f f - m i n ( 8 s / 3 7 s / 2 . 2 5 m s ) d e t o v p 2 . 5 v t o f f b l a n k i n g ( 4 s ) v d e t v a l l e y d e t e c t o r i d e t 1 s t v a l l e y t o f f - m i n + 9 s d e b o u n c e 1 0 0 m s b r o w n o u t c o m p a r a t o r r e c o v e r y o u t p u t o p e n - l o o p ( f b p i n ) o u t p u t s h o r t c i r c u i t ( f b p i n ) d e b o u n c e 7 0 s d e t p i n o v p v d d p i n o v p o u t p u t o v e r p o w e r / o v e r l o a d ( f b p i n ) r e c o v e r y r e c o v e r y 2 . 1 v i z c d 1 v r e c o v e r y l a t c h e d o r r e c o v e r y 3 v l a t c h e d c s o v p r t p i n p r o g o t p r t p i n e x t e r n a l l y t r i g g e r i n g i d e t ? 20 15 f airchild semiconductor corporation www.fairchildsemi.com FL7921R ? rev. 1 . 1 4 f l7921r in tegrated critical - mode pfc and quasi - resonant current - mode pwm lighting controller marking information figure 3. marking diagram pin configuration figure 4. pin configuration pin definitions pin # name description 1 range range pins impedance changes according to the vin pin voltage level. when the input voltage detected by the vin pin is lower than a threshold voltage, it sets to high impedance; whereas it sets to low impedance if input voltage is at a high level. 2 comp output pin of the error amplifier. its a tran s - conductance - type error amplifier for pfc output voltage feedback. proprietary multi - vector current is built - in to this amplifier . t herefore, the compensation for pfc voltage feedback loop allows a simple com pensation circuit between this pin and gnd. 3 inv inverting input of the error amplifier. this pin is used to receive pfc voltage level by a voltage divider and provides pfc output over - and under - voltage protections. 4 cspfc input to the pfc over - curren t protection comparator that provides cycle - by - cycle current limiting protection. when the sensed voltage across the pfc current - sensing resistor reaches the internal threshold (0. 82 v typical), the pfc switch is turned off to activate cycle - by - cycle current limiting. 5 cspwm input to the comparator of the pwm over - current protection and performs pwm current - mode control with fb pin voltage. a resistor is used to sense the switching current of the pwm switch and the sensing voltage is applied to the cspwm pin for the cycle - by - c ycle current limit, current - mode control, and high / low line over - power compensation according to the det pin source current during pwm t on time. continued on the following page 1 - f a i r c h i l d l o g o z - p l a n t c o d e x - 1 - d i g i t y e a r c o d e y - 1 - d i g i t w e e k c o d e t t C d i e - r u n c o d e t - p a c k a g e t y p e ( m = s o p ) m - m a n u f a c t u r e f l o w c o d e 1 6 z x y t t f l 7 9 2 1 r t m g n d d e t f b r t v i n z c d n c h v o p w m v d d o p f c c s p w m c s p f c i n v c o m p r a n g e 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 ? 20 15 f airchild semiconductor corporation www.fairchildsemi.com FL7921R ? rev. 1 . 1 5 f l7921r in tegrated critical - mode pfc and quasi - resonant current - mode pwm lighting controller pin definitions (continued) pin # name description 6 opfc totem - pole driver output to drive the external power mosfet. the clamped gate output voltage is 15. 5 v. 7 vdd power supply. the threshold voltages for startup and turn - off are 18 v and 7. 5 v, respectively. the startup current is less than 30 a and the operating current is lower than 10 ma. 8 opwm totem - pole output generates the pwm signal to drive the external power mosfet. the clamped gate output voltage is 17. 5 v. 9 gnd the power ground and signal ground. 10 det this pin is connected to an auxiliary winding of the pwm transformer through a resistor divider for the following purposes: ? producing an offset voltage to compensate the threshold voltage of pwm current limit for providing over - power compensation. the offset is generated in accordance with the input voltage when the pwm switch is on. ? detecting the valley voltage signal of drain voltage of the pwm switch to achieve the valley voltage switching and minimize the switching loss on the pwm switch. ? providing output over - voltage pro tection. a voltage comparator is built - in to the det pin. the det pin detects the flat voltage through a voltage divider paralleled with auxiliary winding. this flat voltage is reflected to the secondary winding during pwm inductor discharge time. if outpu t ovp and this flat voltage is higher than 2. 5 v, the controller enters auto recovery mode. 11 fb feedback voltage pin. this pin is used to receive the output voltage / current level signal to determine pwm gate duty for regulating output voltage / current . the fb pin voltage can also activate open - loop, overload, and output - short circuit protection if the fb pin voltage is higher than a threshold of around 4. 2 v for more than 50 ms. the input impedance of this pin is a 5 k equivalent resistance. a one - third attenuator is connected between the fb pin and the input of the cspwm/fb comparator. 12 rt adjustable over - temperature protection. a constant current is flowed out of the rt pin. when the rt pin voltage is lower than 0. 8 v (typical), the controller stops all pfc and pwm switching operation and enters auto recovery protection mode. 13 vin line - voltage detection for brown - in / out protections. this pin can receive the ac input voltage level through a voltage divider. the vo ltage level of the vin pin is not only used to control range pins status; (zcd) can also perform brown - in / out protection for ac input voltage uvp. 14 zcd zero - current detection for the pfc stage. this pin is connected to an auxiliary winding coupled to pfc inductor winding to detect the zcd voltage signal once the pfc inductor current discharges to zero. when the zcd voltage signal is detected, the controller starts a new pfc switching cycle. when the zcd pin voltage is pulled to under 0. 2 v (typical), it disables the pfc stage and the controller stops pfc switching. this can be achieved with an external circuit if disabling the pfc stage is desired. 15 nc no connection 16 hv high - voltage startup. hv pin is connected to the ac line voltage through a resistor 100 k ? ? typical) for providing a high charging current to v dd capacitor. ? 20 15 f airchild semiconductor corporation www.fairchildsemi.com FL7921R ? rev. 1 . 1 6 f l7921r in tegrated critical - mode pfc and quasi - resonant current - mode pwm lighting controller absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stres ses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd dc supply voltage 25 v v h v hv pin voltage 500 v v h opfc, opwm pin voltage - 0.3 25.0 v v l other pins (inv, comp, cspfc, det, fb, cspwm, rt) - 0.3 7.0 v v zcd input voltage to zcd pin - 0.3 12.0 v p d power dissipation 800 mw ? ja thermal resistance (junction - to - air) 104 c /w ? j c thermal resistance (junction - to - case) 41 c /w t j operating junction temperature - 40 +150 c t stg storage temperature range - 55 +150 c t l lead temperature (soldering 10 seconds) +260 c esd human body model, jesd22 - a114 (all pins except hv pin) ( 3 ) 5 k v charged device model, jesd22 - c101 (all pins except hv pin) ( 3 ) 2 notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. 2. all voltage values, except differential voltages, are given with respect to gnd pin. 3. all pins including hv pin: cdm=0.5 kv, hbm=1 kv . ? 20 15 f airchild semiconductor corporation www.fairchildsemi.com FL7921R ? rev. 1 . 1 7 f l7921r in tegrated critical - mode pfc and quasi - resonant current - mode pwm lighting controller electrical characteristics v dd =15 v , t j = - 40c ~ 1 2 5 c , unless otherwise specified . symbol parameter conditions min. typ. max. unit v dd section v op continuously operating voltage 25 v v dd - on turn - on threshold voltage 16.5 18.0 19.5 v v dd - pwm - off pwm - off threshold voltage 9 10 11 v v dd - off turn - off threshold voltage t a =25c 6.5 7.5 8.5 v i dd - st startup current v dd =v dd - on - 0. 16 v, gate open 20 30 a i dd - op operating current v dd =15 v; opfc, opwm= 100 k hz; c l - pfc , c l - pwm = 2 nf 10 ma i dd - green green - mode operating supply current (average) v dd =15 v, opwm= 450 hz, c l - pwm = 2 nf 5.5 ma i dd - pwm - off operating current at pwm - off phase v dd =v dd - pwm - off - 0. 5 v 70 120 170 a v dd - ovp v dd over - voltage protection ( auto r ecovery) 23 24 25 v t vdd - ovp v dd ovp de - bounce time 100 150 200 s i dd - latch cspwm pin open protection latch - up holding current v dd =7. 5 v 120 a hv startup current source section v hv - min minimum startup voltage on hv pin 50 v i hv supply current drawn from hv pin v ac = 90 v (v dc = 120 v), v dd = 0 v 1.3 ma hv=500 v, v dd = v dd - off + 1 v 1 a vin and range section v vin - uvp threshold voltage for ac input under - voltage protection 0.95 1.00 1.05 v v vin - re - uvp under - voltage protection reset voltage (for startup) v vin - uvp +0.25 v v vin - uvp +0.30 v v vin - uvp +0.35 v v t vin - uvp under - voltage protection debounce time (no need at startup and hiccup mode) 70 100 130 ms v vin - range - h high v vin threshold for range comparator 2.40 2.45 2.50 v v vin - range - l low v vin threshold for range comparator 2.05 2.10 2.15 v t range range enable / disable debounce time 70 100 130 ms v range - ol output low voltage of range pin i o = 1 ma 0.5 v i range - oh output high leakage current of range pin range= 5 v 20 0 na t on - max - pfc pfc maximum on - time 22 25 28 s continued on the following page ? 20 15 f airchild semiconductor corporation www.fairchildsemi.com FL7921R ? rev. 1 . 1 8 f l7921r in tegrated critical - mode pfc and quasi - resonant current - mode pwm lighting controller electrical characteristics (continued) v dd =15 v , t j = - 40c ~ 1 2 5 c , unless otherwise specified . symbol parameter conditions min. typ. max. unit pfc stage voltage error amplifier section gm transconductance ( 4 ) 100 125 150 mho v ref feedback comparator reference voltage 2.465 2.500 2.535 v v inv - h clamp high feedback voltage range=open 2.70 2.75 2.80 v range=ground 2.60 2.65 2.70 v ratio clamp high output voltage ratio ( 4 ) v invh / v ref , range=open 1.06 1.14 v/v v invh / v ref , range=ground 1.04 1.08 v inv - l clamp low feedback voltage 2.25 2.35 2.45 v v inv - ovp over - voltage protection for inv input range=open 2.90 2.95 v range=ground 2.75 2.80 t inv - ovp over - voltage protection debounce time 50 70 90 s v inv - uvp under - voltage protection for inv input 0.35 0.45 0.55 v t inv - uvp under - voltage protection debounce time 50 70 90 s v inv - bo pwm and pfc off threshold for brownout protection 1.15 1.20 1.25 v v comp - bo limited voltage on comp pin for brownout protection 1.55 1.60 1.65 v v comp comparator output high voltage t a =25c 4.8 6.0 v v oz zero duty cycle voltage on comp pin 1.10 1.25 1.40 v i comp comparator output source current v inv =2. 3 v, v comp =1. 5 v 15 30 45 a v inv =1. 5 v , t a =25c 0.50 0.75 1.00 ma comparator output sink current range=open, v inv =2. 75 v, v comp = 5 v , t a =25c 20 30 40 a range=ground, v inv =2. 65 v, v comp = 5 v 20 30 40 pfc current - sense section v cspfc threshold voltage for peak current cycle - by - cycle limit v comp = 5 v 0.82 v t pd propagation delay 110 200 ns t bnk leading - edge blanking time 110 180 250 ns a v cspfc compensation ratio for thd 0.90 0.95 1.00 v/v continued on the following page ? 20 15 f airchild semiconductor corporation www.fairchildsemi.com FL7921R ? rev. 1 . 1 9 f l7921r in tegrated critical - mode pfc and quasi - resonant current - mode pwm lighting controller electrical characteristics (continued) v dd =15 v , t j = - 40c ~ 1 2 5 c , unless otherwise specified . symbol parameter conditions min. typ. max. unit pfc output section v z pfc gate output clamping voltage v dd = 25 v 14.0 15.5 17.0 v v ol pfc gate output voltage low v dd = 15 v, i o = 100 ma 1.5 v v oh pfc gate output voltage high v dd = 15 v, i o = 100 ma 8 v t r pfc gate output rising time v dd = 12 v, c l = 3 nf, 20~80% 30 65 100 ns t f pfc gate output falling time v dd =12 v, c l =3 nf, 80~20% 30 50 70 ns pfc zero - current detection section v zcd input threshold voltage rising edge v zcd increasing 1.9 2.1 2.3 v v zcd - hyst threshold voltage hysteresis v zcd decreasing 0.25 0.35 0.45 v v zcd - high upper clamp voltage i zcd =3 ma 8 10 v v zcd - low lower clamp voltage 0.40 0.65 0.90 v v zcd - ssc starting source current threshold voltage 1.3 1.4 1.5 v t delay maximum delay from zcd to output turn - on v comp =5 v, f s =60 k hz 5 0 200 ns t restart - pfc restart time 300 500 700 s t inhib inhibit time (maximum switching frequency limit) v comp =5 v 1.5 2.5 3.5 s v zcd - dis pfc enable / disable function threshold voltage 0.1 4 0.20 0.26 v t zcd - dis pfc enable / disable function debounce time v zcd =100 mv 100 150 200 s pwm stage feedback input section a v input - voltage to current - sense attenuation ( 4 ) a v = cspwm / fb , 0 ? 20 15 fairchild semiconductor corporation www.fairchildsemi.com FL7921R ? 5 h y 1.1 10 f l7921r 2 in tegrated critical - mode pfc and quasi - resonant current - mode pwm lighting controller electrical characteristics (continued) v dd =15 v , t j =-40c ~125c , unless otherwise specified. symbol parameter conditions min. typ. max. unit det pin ovp and valley detection section v det - ovp comparator reference voltage 2.45 2.50 2.55 v av open - loop gain ( 4 ) 60 db b w gain bandwidth ( 4 ) 1 mhz t det - ovp output ovp ( a uto r ecovery ) debounce time 100 150 200 s i det - source maximum source current v det = 0 v 1 ma v det - low lower clamp voltage i det = 1 ma - 0.5 - 0.3 - 0. 1 v t valley - delay delay from valley signal detected to output turn - on ( 4 ) 150 200 250 ns t off - bnk leading - edge blanking time for det - ovp (2.5 v) and valley signal when pwm mos fet turns off ( 4 ) 3 4 5 s t time - out time - out after t off - min 8 9 10 s pwm oscillator section t on - max - pwm maximum on time 38 45 52 s t off - min minimum off - time v fb ? v n , t a =25c 7 8 9 s v fb = v g 32 37 42 v n beginning of green - on mode at fb voltage level t a =25c 1.95 2.10 2.25 v v g beginning of green - off mode at fb voltage level t a =25c 1.00 1.15 1.30 v ? 9 g hysteresis for beginning of green - off mode at fb voltage level 0.1 v t starter - pwm start timer (time - out timer) v fb g , t a =25c 1.85 2.25 2.65 ms v fb z v fb - olp , t a =25c 22 28 34 s pwm output section v clamp pwm gate output clamping voltage v dd = 25 v 16.0 17.5 19.0 v v ol pwm gate output voltage low v dd = 15 v, i o = 100 ma 1.5 v v oh pwm gate output voltage high v dd = 15 v, i o = 100 ma 8 v t r pwm gate output rising time c l = 3 nf, v dd = 12 v, 20~80% 80 110 ns t f pwm gate output falling time c l = 3 nf, v dd = 12 v, 20~80% 40 70 ns & |